Dr. Ben Tseng, Chairman & President

Ben Tseng received his B.S. degree from National Taiwan University, and Ph.D. from University of South Carolina, both in electrical engineering. He was an Assistant Professor of Electrical Engineering & Computer Science at Santa Clara University (California) before joining Advanced Micro Devices (AMD) as R&D Department Manager in 1980.  In 1995, he returned to Taiwan to help start a major DRAM company, Powerchip Semiconductor Corporation, as Vice President of R&D.

Dr. Tseng has over 45 years of experience in semiconductor and related high-tech industries in the US and Taiwan, in technical and management positions encompassing R&D, sales & marketing, strategic planning and business consulting.

Dr. Ray Jui-Jen Wu, Vice President & CTO

Ray Jui-Ren Wu has over 25 years of experience in semiconductor R&D, spanning mixed-signal IC design, embedded memory, AI computing architectures, and advanced process technologies.

Ray Wu received his Ph.D. in Electrical Engineering from National Tsing Hua University, Taiwan. His research focuses on neuromorphic AI systems, Compute-in-Memory (CIM) architecture/circuit design, embedded memory technologies, and analog/mixed-signal IC design. He has published papers in top-tier conferences, including ISSCC, VLSI Symposium, and IEDM, as well as in the Journal of Solid-State Circuits (JSSC), TCAS-I, TCAS-II, and holds more than 80 patents in circuit design and semiconductor technologies.

Dr. Wu worked at the IC Design Center of Seiko Epson, Taiwan, where he focused on MCU and mixed-signal design. He later joined Taiwan Semiconductor Manufacturing Company (TSMC), where he spent more than 20 years leading memory design, AI system architecture, and advanced semiconductor technology development. He held several key technical and management positions, including Manager of Corporate Research and memory library design. In recognition of his technical contributions, he received multiple TSMC awards, including the Best Patent Award, Best Innovation Award, and Best Trade Secret Award.

Dr. Wu currently serves as a Technical Program Committee (TPC) Member of IEEE A-SSCC and review committee for the IEEE Journal of Solid-State Circuits (JSSC) and IEEE ISCAS. He is an IEEE Senior Member.

Singhan Wang, Digital Design, Manager

Singhan Wang holds an MS degree in Electrical Engineering from National Sun Yat-Sen University, Taiwan. He has over 15 years of experience in digital system development specializing in the design of power management systems, embedded firmware development, and ASICs. His technical expertise and responsibilities mostly focused on digital design in advanced technology nodes, where he manages the complete front-to-back development cycle—from writing clean, synthesis-friendly Verilog RTL for fast-charge power protocols (such as PD, SCP/FCP, and UFCS), digital PWM generation, and precision closed-loop controller logic to building robust validation environments. His system integration capabilities cover complex SoC architectures including ARM Cortex-M0 and 8051 MCU subsystems, memory interfaces (ROM, SRAM, and IRAM controllers), and high-resolution ADC control logic.

By bridging the gap between digital system architectures, analog front-ends, and backend physical design teams, Singhan consistently resolves complex layout constraints to achieve timing closure, bringing designs from initial block-level specification to successful silicon verification and mass production.

Rory Wen, Analog Design, Manager

Rory Wen is a highly experienced Analog Design Engineer with over 20 years of hands-on expertise in transistor-level design, mixed-signal block implementation, and complex full-chip SoC integration. He specializes in the design and validation of high-performance Power Management ICs (PMICs), display driver systems (Mini LED & EPD), and motor controller systems.

Rory received an MS degree in Electrical Engineering at National Sun Yat-Sen University.  His study was focused on analog IC design.  His core technical expertise lies in bridging structural circuit simulation with physical silicon performance. He has an extensive track record of managing complete IC design flows—from initial schematic design and transient simulation to chip layout oversight, static/dynamic validation, and post-silicon debug. He is highly skilled in resolving physical layout parasitic issues, ensuring signal integrity across multi-domain SoCs, and coordinating with test engineers to align custom design parameters with strict Chip Probing (CP) and Final Test (FT) limits.

Richard Chen, Physical Design, Manager

Richard Chen is a veteran IC Layout professional with over 20 years of experience in full-custom IC layout design. He specializes in the highly intricate domain of Memory Compilers (including 1P/2P SRAM, TCAM, and VROM), Cell Libraries, and IO ESD layout. Over his distinguished career, Richard has developed a deep understanding of process technologies, spanning from legacy 0.32µm planar nodes to the most advanced FinFET and next-generation nodes like TSMC’s N3E, N3, and N4P, as well as Samsung’s N5 process.

With extensive experience at tier-1 design companies and leading IP providers including MediaTek and M31 Technology, Richard possesses an exceptional ability to optimize Power, Performance, and Area (PPA). He stands out for his technical precision in area compression and his proactive approach to managing resistance/capacitance (R/C) effects and Layout Dependent Effects (LDE), directly contributing to maximized silicon yield and optimal product performance.

Ken Chang, Software & Systems, Manager

Ken Chang is an experienced Software and System Leader with over 30 years of expertise in enterprise infrastructure, EDA computing environments, and digital transformation for semiconductor and high-tech industries. He specializes in architecting secure, scalable, and highly available platforms that support mission-critical IC design, engineering collaboration, and business continuity.

His technical expertise spans enterprise infrastructure, cloud technologies, cybersecurity, virtualization, network architecture, and EDA platform deployment. He also possesses extensive experience in enterprise system integration, workflow automation, and engineering platform optimization, enabling organizations to improve operational efficiency while maintaining robust security, reliability, and governance.

By bridging enterprise infrastructure, engineering platforms, and business operations, Ken consistently delivers reliable technology solutions that enhance engineering productivity, streamline organizational workflows, and accelerate digital transformation. His strategic vision and hands-on leadership have helped organizations build resilient, cost-effective platforms that support long-term innovation and sustainable business growth.